[SDDCS 2016] Leveraging Semantic Links for High Efficiency Page-Level FTL Design (ICDCS 2016 Workshop)

NAND Flash Solid State Disks (SSDs) are gaining

tremendous popularity in today’s storage market due to their

low energy consumption and high I/O performance. To mask

the unique erase-before-write feature of NAND flash, the Flash

Translation Layer (FTL) in SSD redirects the incoming writes

to a free physical address and manages a logical to physical

address mapping table. However, the increasing capacity of SSD

has lead to mapping tables large in size, which not only impose

high pressure on the efficiency of page-level address mapping,

but also induces significant performance degradation to SSD.

To overcome this problem, Correlation-Aware Page-level FTL

(CPFTL) is proposed in this work. CPFTL uniquely leverages

the inherent data semantics in enterprise workloads to optimize

mapping table cache management. First, a correlation-aware

mapping table is developed based on the correlation in read

operations. We then propose a correlation prediction table to

support fast mapping entry lookup in correlation-aware mapping

table. Our experimental results show that CPFTL reduces the

average response time by 63.4% for read dominant workloads

and 32.9% for transaction workloads.