[EuroSys 2015] An Efficient Page-level FTL to Optimize Address Translation in Flash Memory

You Zhou, Fei Wu, Ping Huang, Xubin He, Changsheng Xie, Jian Zhou. EuroSys 2015.

Flash-based solid state disks (SSDs) have been very popular in consumer and enterprise storage markets due to their high performance, low energy, shock resistance, and small sizes. However, the increasing SSD capacity imposes great pressure on performing efficient logical to physical address translation in a page-level flash translation layer (FTL). Existing schemes usually employ an on-board RAM cache for storing mapping information, called mapping cache, to speed up address translation. Since only a fraction of the mapping table can be cached at a time due to limited cache space, a large number of extra operations in flash memory are required for cache management and garbage collection, degrading performance and lifetime. In this paper, we first apply analytic models to investigate the key factors that incur extra operations. Then, we propose an efficient page-level FTL, named as TPFTL, which employs two-level LRU lists to organize cached mapping entries to minimize extra operations. Inspired by the models, we then design a workload-adaptive loading policy combined with an efficient replacement policy to increase the cache hit ratio while reduce writebacks of replaced dirty entries. Finally, we evaluate TPFTL using extensive trace-driven simulations. Our evaluation results show that compared to the state-of-the-art FTLs, TPFTL reduces random writes caused by address translation by an average of 62% and improves response time by up to 24%.