The Dirty-Block Index on ISCA 2014.
This paper is about dirty block management of on-chip caches. Existing cache organization mix dirty block and clean block in a single list and use a tag entry to distinguish them. The problem of current solution exhibits in 1) determine if a block is dirty, and 2) identify the list of spatial co-located dirty blocks. In this paper, the authors remove the dirty bit in the tag entries and organize them differently in a separate structure, which is called Dirty-Block Index (DBI).
The DBI Enabled the following Optimizations:
Excient DRAM-Aware Aggressive Writeback
In DRAM… Requests to the row buffer (row buffer hits) are much faster and more efficient than other requests (row buffer misses)… filling the write buffer with blocks from the same DRAM row will lead to a faster and more efficient writeback phase.
This is very similar to the motivation of Batch cache update in SSD.
Efficient Cache Lookup Bypass
If an application’s miss rate exceeds a threshold (0.95, in our experiments), all accesses of the application (except those that map to the sampled sets) are predicted to miss in the cache in the next epoch.
Reducing ECC Overhead
… only dirty blocks require a strong ECC; clean blocks only require error detection. This is because, if an error is detected in a clean block, the block can be retrieved from the next level of the memory hierarchy